ADCs are employed in a variety of applications. In particular, high performance focal plan array (FPA) applications require wide-area coverage, high signal-to-noise-ratios (SNR), high spatial resolution, and high frame rates in various combinations. Conventional FPAs are not particularly well-suited to satisfying combinations of the above requirements. Conventional FPAs typically provide analog readouts, with the analog signals generated at the pixel level converted to digital signals “off chip.” Once converted off-chip, the digital signals may be processed according to the demands of a particular application. Specific analog designs can target (and possibly achieve) one or more requirement, but fail when simultaneously targeting the most aggressive design parameters for imaging applications, such as long-wave infrared imaging (LWIR) applications.
Fundamental limitations on achievable well depth (with concomitant limitations on capacitor size), and the readout noise floor, limit practical scalability of conventional designs. Capacitor size limitations require unnecessarily high frame rates to avoid saturating pixels. Electronics noise and ringing limit the amount of data that can be transmitted on a single output lap to maintain the needed SNR and dynamic range. Attempting to scale conventional analog technology to meet the most demanding requirements leads to a high-power-consumption FPA with many data output taps. This in turn leads to a large, massive, and complex sensor system.
ADCs that are capable of converting a number of signals and a communication structure for manipulating the resulting digital counts in real-time to achieve signal processing functionality, would therefore be highly desirable and may find application in a number of systems, including focal plane arrays.
An apparatus in accordance with the principles of the present invention includes a two-dimensional array of analog to digital converters (ADCs). In an illustrative embodiment, the ADCs are all self-contained. That is, in such an embodiment, each of the ADCs is capable of operating without signaling, such as an analog ramp signal, or analog reference signal supplied by an outside source. Each of the ADCs within the array may include circuitry to convert a current mode signal to a voltage signal for conversion. In such an embodiment, a capacitor may be employed to integrate charge from the current mode signal and the capacitor and ADC architecture may be selected to determine the least significant bit of each of the ADCs. In such an embodiment, a counter may be employed to determine the most significant bit of each of the ADCs.
An ADC array in accordance with the principles of the present invention may include circuitry that permits the orthogonal transfer of conversion results throughout the array. Such an array may include circuitry that permits the array to convert the plurality of analog signals to digital signals, and then perform digital processing on the resulting digital signals. The processed signals may then be sent, for example, to an analyzer for computation and analysis. In accordance with the principles of the present invention, digital signal processing functions included within the ADC array may include digital filtering, such as spatial or temporal filtering, autonomous digital threshold detection, time-domain filtering, including high-pass or low-pass filtering, and data compression, using, for example, Decimation.
Additionally, an ADC array in accordance with the principles of the present invention may be configured to accept and convert analog signals that are spatially mapped to the arrangement of ADCs within the array. The spatial mapping may be, for example, a one-to-one mapping, with signals arriving at the top left ADC within the array originating at a corresponding location within an array of signals, the signal arriving at the bottom right ADC within the array originating at a corresponding location within an array of signals, and so on. In an integrated circuit embodiment, an entire ADC array may be implemented using a silicon CMOS process, for example.
An ADC array in accordance with the principles of the present invention may be employed as a readout integrated circuit that operates in conjunction with, for example, a photosensor array. In such an embodiment, each of the ADCs within the array may occupy no more area than the area consumed by each of the corresponding photosensors. A readout integrated circuit that employs an ADC array in accordance with the principles of the present invention may foe combined with a photosensor array, using hybrid techniques, such as bump-bonding, for example, to form a novel focal plane array.
In an Illustrative embodiment an all-digital readout Integrated circuit (ROIC) in accordance with the principles of the present invention may be used in conjunction with a cryogenically cooled infrared detector array, with connections between the detector array and the ROIC made via indium bump bonding. The hybrid device thus formed is referred to herein as a digital focal plane array (DFPA). In an illustrative embodiment, the detector array senses incoming optical radiation in the infrared region of the spectrum (2-20 microns) using photodiodes to create currents that are proportional to the optical radiation impinging on the photodiodes. That is, each photodiode (also referred to herein as a pixel) in the detector array produces a current that is proportional to the photon flux impinging upon it. Each photodiode in the array has associated with it a unit cell in the ROIC. The current in each photodiode is collected in the photodiode's associated unit cell within the ROIC. The unit cell electronics integrate the charge and produces, via an analog to digital converter (ADC), a digital number (DN) that is proportional to the total charge accumulated over the frame period. In this illustrative embodiment, the DN for each pixel is then shifted to the edge of the ROIC and multiplexed with other DNs associated with other pixels for transfer off the array. By digitizing the signal while photoelectrons are being collected, rather than after charge accumulation, the need for large charge storage capacitors and highly linear analog electronics can be eliminated. The power dissipation and noise problems associated with a conventional, analog readout, approach are also greatly reduced. Additionally, this approach permits operation with circuitry that operates from a lower level power supply, because the dynamic range requirements associated with conventional systems needn't be maintained. Permitting operation with tower-level power supplies permits the use of Integrated Circuit processes that offer much smaller feature sizes, thereby further enabling the ADC and readout circuitry to be packed within an area less than or equal to the area consumed by the associated detector pitch, also referred to as the pixel pitch. Simplifying the unit cell preamplifier offers considerable power savings for large arrays.
In this illustrative embodiment, the capacitor size defines the least significant bit of the ADC. In this way, the size of the capacitor may be kept to a minimum, thereby significantly reducing the area required for the analog to digital conversion. In this illustrative embodiment, the analog to digital conversion is achieved via a voltage-to-frequency converter in which a predetermined amount of photocurrent charges the capacitor to a level that produces an output pulse and resets the capacitor. The output pulses are counted and the count in a given time period corresponds to the amount of photocurrent and, correspondingly, the light flux impinging on the associated photodiode. In this way, the illustrative embodiment of a DFPA in accordance with the principles of the present invention digitizes the signal while photoelectrons are being collected, rather than after charge accumulation.
A system and method in accordance with the principles of the present invention may be employed to form a DFPA that includes a Nyquist-rate ADC formed wholly within the area of the ADC's associated detector, or pixel pitch. In such an embodiment, each of the ADCs may operate independently of the other ADCs associated with other photodiodes.
An ADC array in accordance with the principles of the present invention may be particularly well-suited for use in an imaging system. In such an implementation, an imaging system might employ an ADC array in accordance with the principles of the present invention in conjunction with a sensor array, such as a photosensor array, to gather and process analog signals. The analog signals subject to processing in such an implementation may represent electromagnetic radiation characterized by any wavelength, and need not be limited to signals that might conventionally be associated with “imaging.” That is, in addition to signals that represent photon flux, the signals may, directly, or indirectly, represent, chemical or biological content, for example. Such an imaging system may employ an ADC array in accordance with the principles of the present invention to, in addition to converting analog signals to digital, perform digital signal processing operations on the converted signals. Further computations and analysis may be performed by the imaging system on the output of the ADC array. An imaging system in accordance with the principles of the present invention would be particularly suited to use in industrial inspection, surveillance, process control, biological research, chemical research, pharmaceuticals, medical imaging, remote sensing, and astronomy, for example.
A system in accordance with the principles of the present invention integrates a focal plane array with digital readout circuitry. In an illustrative embodiment, the focal plane array includes an army of optical diodes, with each diode defining a pixel. In accordance with the principles of the present invention, circuitry is included in the focal plane array to convert the signal from each diode to a digital signal. Each pixel includes an analog to digital converter (ADC) that is formed within the same area as the photodiode. In an illustrative embodiment, the digital signals produced by the ADCs at each photodiode are routed off-chip. The density of the photodiode array is not limited by the ADC and associated circuitry at each pixel location. Consequently, extremely high-resolution imaging may be achieved by a digital focal plane array (DFPA) In accordance with the principles of the present invention.
An apparatus and method in accordance with the principles of the present invention may also be employed by a DFPA to incorporate on-chip processing to further enhance the DFPA's performance. Such processing may include: digital spatial/temporal filtering that may be implemented by pixel binning whereby image resolution may be traded for dynamic range and/or frame rate; autonomous digital threshold detection that may be used in launch detection or flash detection, for example; time domain digital filtering, such as high-pass or low-pass filtering that may be employed to identify fast- or slow-moving objects; time domain image detection and jitter compensation that, for example, that shifts digital row data synchronously with ground speed and provides image stabilization for field of view jitter; data compression to reduce raw data rate using, for example, decimation; and the use of edge enhancement, such as octonet edge enhancement to aid in feature identification.
A sensor that employs a DFPA in accordance with the principles of the present invention may operate in a variety of modes. In an unmanned aerial vehicle (UAV) application, for example, such a sensor may operate in: a high-resolution day/night panchromatic surveillance mode; a low resolution day/night rapid panchromatic battlefield monitoring, flash/launch detection mode; a low resolution day/night hyper-spectral effluence classification and atmospheric condition mode; and a time domain imaging (TDI) mode for “push broom” terrain mapping. An apparatus and method in accordance with the principles of the present invention may be particularly well-suited for use in a large format digital focal plane array (DFPA). Such a DFPA could provide high-resolution wide-area coverage and would thereby find application in air and space intelligence, surveillance, and reconnaissance (ISR). In such an application the DFPA could drastically reduce the number of assets required for global persistent day/night surveillance and launch defection and fully utilize diffraction-limited resolution. The DFPA could also be employed in atmospheric monitoring, providing the ability to detect the initiation of severe weather events on a global scale, thereby lengthening warning times that might allow those in the paths of storms to avoid or ameliorate disaster. A DFPA in accordance with the principles of the present invention may also be used in the detection and identification of chemical agents, for example, in the search for weapons, including weapons of mass destruction. Such detection and identification of chemical agents may also be employed in chemical, medical, or industrial systems in large-scale industrial inspection and massive parallel molecular process monitoring applications.
An ADC array in accordance with the principles of the present invention may incorporate digital signal processing circuitry in the array. In an illustrative embodiment, an array includes an up/down counter at each ADC location and circuitry for the orthogonal shifting of the digital output of each ADC. By controlling the accumulation time, the number and direction of counts, and the number and direction of shifts, the ADC array itself may be employed as an array-wide digital signal processor.
An imaging system that incorporates an ADC array in accordance with the principles of the present invention may be configured to operate, for example, as a camera (in any of a number of electromagnetic bands, including, but not limited to, the visual and infrared) as a surveillance system, as a robotic control system, or as a chemical or biological detection or identification system.